Researchers at the University of Illinois have developed a new thermal control method for gallium nitride (GaN).

GaN transistors have higher power densities than conventional silicon transistors and can operate at higher temperatures (below 500 ° C), but GaN transistors, like all semiconductors, also generate excessive heat, which limits their performance.

Cooling methods based on heat sinks and fans add cost and volume. Now, a team of researchers at the University of Illinois’ micro-nanotechnology labs has created a new approach that claims to be simple and low-cost. smbd-101

Using computer-aided design, Kan Bailam’s team has demonstrated that the thickness of the GaN layer plays a large role in overheating, affecting the thermal expectations and final performance of the device.

“Thinner and colder,” says Byram, “traditional GaN transistors are deposited on thick substrates (such as silicon, silicon carbide), but this is not an ideal thermal conductor.” The challenge, he says, Epitaxial mismatches on the substrate, which results in devices that are tens of microns thick, and in many cases hundreds of microns.

“This has a very poor effect on heat dissipation, taking into account the heat source as the gate narrows at the submicron level,” Beylam said. The use of novel semiconductor release methods, such as smart cutting and peeling, a GaN transistor that can be released from the remaining epitaxial and thicker substrates, can benefit from improved thermal control. mt47h64m16hr

“By refining the device layer, you can reduce the high-power GaN transistor 50 degrees Celsius hot spot temperature.” Byram said.

The research leader Kehun Parker believes there is a limit to device thickness. “If you reduce too much, you get the opposite effect, actually increasing the temperature inside the device,” Parker said. For a typical device, the optimum thickness is about one micron.

The work, they say, is important because it provides thermal-design guidelines for GaN-based transistors. The optimal layer size is closely related to the device interface thermal resistance (TBR), which is a condition for the existence of GaN epitaxial layers and other interfaces.

“We determined the optimal thickness of the GaN transistor’s hot-spot temperature, depending on the value of the TBR, and the size of the layer depends on how the device will be used.” If it is for higher power applications, then ideally you need more Thin, sub-micron thick layer. ”

The next step for the Illinois team is to study the electrical properties of GaN layers, such as engineering diamonds and epitaxial graphene, before actually fabricating GaN transistors on substrates.

The Illinois study was funded by the Air Force Academy of Science (AFOSR) Youth Research Project Grant No. FA9550-16-1-0224; the results were published in the October 10, 2016 Applied Physics Letters B1 page.