The memory industry is in a phase of strong growth. Yole predicts in its 2017 Memory Packaging Market and Technology report that the total memory market will grow at a CAGR of about 9% between 2016 and 2022, to reach US $ 135 billion by 2022 and to make up about 95% of DRAM and NAND market share %. In addition, the imbalance between supply and demand is driving up the price of memory semiconductor chips, resulting in a record profit for memory IDM vendors!
The demand for memory comes from all walks of life, especially in the mobile and computing (mostly server) markets. On average, each smartphone’s DRAM memory capacity will more than tripling and is expected to reach around 6GB by 2022, with each smartphone’s NAND memory capacity more than doubling and projected to reach 150GB by 2022 . For servers, it is expected that by 2022 DRAM memory capacity will reach more than 0.5TB, enterprise-level market NAND NAND memory capacity of SSD will be up to 5TB or more. The growth drivers for these markets come from deep learning, data centers, networks, AR / VR and autopilot.
DRAM and NAND capacity requirements for smartphones and servers
The automotive market, which typically uses low-megabyte memory, will see DRAM memory dominated by autonomous driving and car infotainment. In addition, the NOR flash memory market is recovering and is expected to grow at an astonishing 16% CAGR. It is estimated that it will reach 4.4 billion U.S. dollars in 2022, mainly due to new developments such as AMOLED displays, touch display driver ICs and industrial Internet of Things Application of the field.
On the supply side, there is a shortage of DRAM and NAND memory supplies due to vendor consolidation and technical challenges that make advanced nodes harder to implement and require significant investments in moving from 2D to 3D NAND. DRAM makers want to maintain high product prices and profitability in order to rationalize their huge capital expenditures in advanced node migration, and therefore tend not to increase production capacity.
Memory chips use a variety of packaging technologies, from leadframes to through-silicon vias (TSVs)
There are a variety of packaging options for memory chips, ranging from pin-count, small outline SOPs to pin-count TSVs, and the choice of these technologies depends on density, performance, and Cost and other product requirements. Yole analysis identified five core memory chip packaging platforms: leadframe, wire-bond BGA, flip-chip BGA, wafer level chip scale package (WLCSP), TSV. Each technique includes many different variations and different terminology. We expect CAGR of the entire memory chip packaging market to grow from 4.6% in 2016-2022 to more than 25 billion in 2022.
The type of memory chip package
In 2016, wire-bonded BGA accounted for more than 80% of the memory chip package market share. Also in 2016, the flip-chip BGA has started to enter the DRAM memory chip package market and is expected to grow at a CAGR of 20% in the next five years, accounting for about 10% of the market for the entire memory chip package market. With the promotion of high bandwidth demand, the application of DRAM PC / server field is increasing day by day, has promoted the flip-chip market growth. Samsung has converted more than 90% of its DRAM chip packages into flip-chips and SK hynix has also begun to transition, and other vendors will gradually adopt flip-chips in the future. In fact, we believe that all DDR5 memory used for PC / server will eventually use flip chip.
Through silicon (TSV) is being used in high-bandwidth memory chips due to the high latency of high bandwidth and memory chips for high performance computing in a variety of applications. The TSV market will account for less than 1% of the memory chip packaging market in 2016, but with a CAGR of over 30% over the next five years. It is expected that TSV market share will reach 2022 8%. Meanwhile, the wafer-level chip scale package (WLCSP) will be adopted by NOR flash memory and niche market memories (EEPROMs / EPROM / ROM) and is expected to grow at a CAGR of over 10%. However, by 2022, wafer- Packaging (WLCSP) market share of less than 1%.
For mobile applications, memory chip packaging will primarily be held on wire-bonded BGA platforms, however, and will soon begin to move toward multi-chip packaging (ePoP) for high-end smartphones. The main requirement of NAND flash memory chips is low cost and high storage density. NAND uses a wire bond stack to provide high density in a single package.
NAND flash chip packages will remain in wire-bonded BGA form and will not migrate to flip-chip. However, Toshiba will begin using silicon vias (TSVs) in NAND flash memory chips to increase the data transfer rates for high-end applications. After Toshiba, we believe Samsung Electronics and SK hynix will introduce silicon-on-a-chip (TSV) packaged NAND chips.
The value of memory chip package is high, mainly by IDM “control”
The market size of memory chip packaging in 2016 is about 20 billion U.S. dollars. While many outsourced semiconductor package test vendors (OSATs) are involved in the memory chip packaging business, more than 80% of the packages are still in-house by memory chip IDM vendors. The world’s leading IDM vendors have a wealth of knowledge in packaging, have accumulated years of project experience, and have a strong internal manufacturing capacity.
2016 ~ 2022 memory chip packaging market
OSAT vendors are affected by IDM vendors and have limited opportunity to package their business in memory chips. However, many Chinese companies are investing more than 50 billion U.S. dollars into the field of memory. Unlike the world’s leading IDM vendors, emerging Chinese vendors lack experience in memory chip packaging and will outsource their packaging operations to OSAT vendors.
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